Tracks microarchitecture changes and their impact on IPC, cycle count, and stall breakdown.
make coremark-npc32 ARGS="-b -n" and make microbench-npc32 ARGS="-b -n" (RV32EM, npc standalone)ISSUE_WIDTH=1, ROB_SIZE=8, RS_SIZE=4, IOQ_SIZE=4, SQ_SIZE=8, PHY_SIZE=64, L1I: 64x4w 1-way, L1D: 32x2w 2-way| Commit | Change | #Cycle | #Inst | IPC | IFU, % | EX|RS, % | EX|IoQ, % | L1D, % | SQ, % | Bubble, % | | ——– | ———————– | ——- | ——- | —– | —— | ——— | ———- | —— | —— | ——— | | 8bd5a63a | OoO baseline (PRF->top) | 5918107 | 2993965 | 0.506 | 0, 0 | 1e6, 17 | 2e6, 35 | 9e4, 2 | 6e6,99 | 3e6, 49 | | 4190ade0 | SRAM pre-read 1 | 6784901 | 2993965 | 0.441 | 0, 0 | 5e5, 8 | 2e6, 25 | 1e5, 1 | 7e6,99 | 4e6, 56 | | a9ca5680 | SQ bypass + STL fwd 2 | 6753082 | 2993965 | 0.443 | 0, 0 | 4e5, 6 | 2e6, 22 | 1e5, 1 | 7e6,99 | 4e6, 56 | | f14efbe6 | L1D 2w+RMW, TLB/PTW 3 | 6752062 | 2993966 | 0.443 | 0, 0 | 4e5, 6 | 2e6, 22 | 9e4, 1 | 7e6,99 | 4e6, 56 | | c359a54c | L1I 4w, dual cm, SQ 4 | 4889011 | 2993938 | 0.612 | 2e6,34 | 5e5, 9 | 2e6, 31 | 9e4, 2 | 0e0, 0 | 2e6, 45 | | a4843255 | BPU, RN pipe 5 | 4910745 | 2996920 | 0.610 | 2e6,34 | 5e5,10 | 2e6, 31 | 1e5, 2 | 0e0, 0 | 2e6, 46 | | 66ebaf1b | BPU infra 6 | 4910725 | 2996919 | 0.610 | 2e6,34 | 5e5,10 | 2e6, 31 | 1e5, 2 | 0e0, 0 | 2e6, 46 |
| Commit | Change | #Cycle | #Inst | IPC | IFU, % | EX|RS, % | EX|IoQ, % | L1D, % | SQ, % | Bubble, % | | ——– | ———————– | —— | —— | —– | —— | ——— | ———- | —— | —— | ——— | | 8bd5a63a | OoO baseline (PRF->top) | 606833 | 373461 | 0.615 | 0, 0 | 9e4, 14 | 3e5, 46 | 2e4, 3 | 6e5,99 | 2e5, 38 | | 4190ade0 | SRAM pre-read 1 | 749629 | 373461 | 0.498 | 0, 0 | 6e4, 8 | 2e5, 30 | 2e4, 3 | 7e5,99 | 4e5, 50 | | a9ca5680 | SQ bypass + STL fwd 2 | 742618 | 373461 | 0.503 | 0, 0 | 4e4, 5 | 2e5, 27 | 2e4, 3 | 7e5,99 | 4e5, 50 | | f14efbe6 | L1D 2w+RMW, TLB/PTW 3 | 740918 | 373462 | 0.504 | 0, 0 | 4e4, 5 | 2e5, 26 | 2e4, 2 | 7e5,99 | 4e5, 50 | | c359a54c | L1I 4w, dual cm, SQ 4 | 627667 | 373462 | 0.595 | 2e5,34 | 4e4, 7 | 2e5, 31 | 2e4, 3 | 0e0, 0 | 3e5, 46 | | a4843255 | BPU, RN pipe 5 | 638491 | 373462 | 0.585 | 2e5,34 | 4e4, 7 | 2e5, 30 | 1e4, 2 | 0e0, 0 | 3e5, 47 | | 66ebaf1b | BPU infra 6 | 637357 | 373461 | 0.586 | 2e5,34 | 4e4, 7 | 2e5, 31 | 1e4, 2 | 0e0, 0 | 3e5, 47 |
| Column | Description |
|---|---|
| Commit | Short git hash |
| Change | Brief description of the microarchitecture change |
| #Cycle | Total simulation cycles |
| #Inst | Total committed instructions |
| IPC | Instructions per cycle |
| IFU, % | Stall cycles from instruction fetch, percentage of total |
| EX|RS, % | Stall cycles from reservation station (ALU/MUL), percentage |
| EX|IoQ, % | Stall cycles from in-order queue (LSU/CSR), percentage |
| L1D, % | Stall cycles from L1D cache misses, percentage |
| SQ, % | Stall cycles from store queue, percentage |
| Bubble, % | Pipeline bubble cycles, percentage |