Performance Iterations

Legacy Version: PROFILE.md

Tracks microarchitecture changes and their impact on IPC, cycle count, and stall breakdown.

Benchmark: make coremark-rv32 ARGS="-b -n" and make microbench-rv32 ARGS="-b -n" (RV32EM, npc standalone)
Config: unless a row or footnote says otherwise, benchmark rows use the dual-issue NPC path. Current default RTL/config is ISSUE_WIDTH=2, ROB_SIZE=64, RS_SIZE=8, RIQ/IIQ=8, IOQ_SIZE=8, SQ_SIZE=16, PHY_SIZE=128, L1I: 32 sets × 16 instruction words × 2 ways (4 KiB, 64-byte lines), L1D: 16 sets × 16 RV32 words / 8 RV64 words × 2 ways (2 KiB, 64-byte lines), TAGE direction predictor, and RAPT_L2_EN disabled by default (the instantiated L2 stage is passthrough unless that macro is defined).

Benchmark Results

CoreMark

Commit	Change	#Cycle	#Inst	IPC	IFU, %	EX\|RS, %	EX\|IoQ, %	L1D, %	SQ, %	Bubble, %
1245810	OoO baseline (PRF->top)	5918107	2993965	0.506	0, 0	1e6, 17	2e6, 35	9e4, 2	6e6,99	3e6, 49
a9ca568	SRAM pre-read 1	6784901	2993965	0.441	0, 0	5e5, 8	2e6, 25	1e5, 1	7e6,99	4e6, 56
40e3c86	SQ bypass + STL fwd 2	6753082	2993965	0.443	0, 0	4e5, 6	2e6, 22	1e5, 1	7e6,99	4e6, 56
f14efbe	L1D 2w+RMW, TLB/PTW 3	6752062	2993966	0.443	0, 0	4e5, 6	2e6, 22	9e4, 1	7e6,99	4e6, 56
2529b49	L1I 4w, dual cm, SQ 4	4889011	2993938	0.612	2e6,34	5e5, 9	2e6, 31	9e4, 2	0e0, 0	2e6, 45
905735e	Pipe, BPU infra 5	4910725	2996919	0.610	2e6,34	5e5,10	2e6, 31	1e5, 2	0e0, 0	2e6, 46
a71d54b	Dual fetch/decode 6	3718623	2903330	0.781	9e5,23	7e5,19	2e6, 42	1e5, 3	0e0, 0	2e6, 43
ce2f2a1	Zba/Zbb/Zbs+Zicond 7	3678424	2860965	0.778	8e5,21	7e5,19	2e6, 42	1e5, 3	0e0, 0	2e6, 44
e913241	Zbc + ROB fix 8	3681752	2860946	0.777	8e5,21	7e5,19	2e6, 42	1e5, 3	0e0, 0	2e6, 44
dfca64e	2ALU pMUL OoO LSU 9	2869704	2530446	0.882	7e5,25	1e6,36	1e6, 51	9e4, 3	0e0, 0	1e6, 36
76143bb	RAS-4 + TAGE 10	16958705	15914408	0.938	4e6,26	7e6,40	9e6, 53	3e5, 2	0e0, 0	5e6, 32
current	Default worktree 12	14321377	15914407	1.111	5e5, 4	0e0, 0	1e7, 72	1e5, 1	0e0, 0	5e6, 32

MicroBench

Commit	Change	#Cycle	#Inst	IPC	IFU, %	EX\|RS, %	EX\|IoQ, %	L1D, %	SQ, %	Bubble, %
1245810	OoO baseline (PRF->top)	606833	373461	0.615	0, 0	9e4, 14	3e5, 46	2e4, 3	6e5,99	2e5, 38
a9ca568	SRAM pre-read 1	749629	373461	0.498	0, 0	6e4, 8	2e5, 30	2e4, 3	7e5,99	4e5, 50
40e3c86	SQ bypass + STL fwd 2	742618	373461	0.503	0, 0	4e4, 5	2e5, 27	2e4, 3	7e5,99	4e5, 50
f14efbe	L1D 2w+RMW, TLB/PTW 3	740918	373462	0.504	0, 0	4e4, 5	2e5, 26	2e4, 2	7e5,99	4e5, 50
2529b49	L1I 4w, dual cm, SQ 4	627667	373462	0.595	2e5,34	4e4, 7	2e5, 31	2e4, 3	0e0, 0	3e5, 46
905735e	Pipe, BPU infra 5	637357	373461	0.586	2e5,34	4e4, 7	2e5, 31	1e4, 2	0e0, 0	3e5, 47
a71d54b	Dual fetch/decode 6	506854	364937	0.720	1e5,27	6e4,12	2e5, 46	1e4, 3	2e4, 3	2e5, 47
ce2f2a1	Zba/Zbb/Zbs+Zicond 7	501128	340182	0.679	1e5,25	7e4,13	2e5, 44	1e4, 3	2e4, 4	2e5, 49
e913241	Zbc + ROB fix 8	500857	340204	0.679	1e5,28	7e4,13	2e5, 44	1e4, 3	2e4, 3	2e5, 49
dfca64e	2ALU pMUL OoO LSU 9	460943	339907	0.737	1e5,27	1e5,26	2e5, 46	2e4, 4	0e0, 0	2e5, 46
76143bb	RAS-4 + TAGE 10	459530	339907	0.740	1e5,25	1e5,25	2e5, 44	2e4, 3	0e0, 0	2e5, 46
current	Default worktree 12	402118	339863	0.845	3e4, 7	0e0, 0	3e5, 72	1e4, 3	0e0, 0	2e5, 46

Column Description

Column	Description
Commit	Short git hash
Change	Brief description of the microarchitecture change
#Cycle	Total simulation cycles
#Inst	Total committed instructions
IPC	Instructions per cycle
IFU, %	Stall cycles from instruction fetch, percentage of total
EX\|RS, %	Stall cycles from reservation station (ALU/MUL), percentage
EX\|IoQ, %	Stall cycles from in-order queue (LSU/CSR), percentage
L1D, %	Stall cycles from L1D cache misses, percentage
SQ, %	Stall cycles from store queue, percentage
Bubble, %	Pipeline bubble cycles, percentage

STA Results

Static timing / area / power across PDKs via make sta (OpenROAD/yosys-opensta flow). One row per commit per ISA; Fmax in MHz (post-synth, worst corner), Area in um^2, Power in W. Columns grouped by PDK (nangate45 / asap7 / sky130hd).

The historical [11] STA row is run with the small (single-issue, low-area) uarch preset (make sta RAPT_CONFIG=small). Earlier rows ([9], [10]) used the default (dual-issue OoO) preset, so [11] is not directly comparable in area/Fmax.

RV32

Commit	Change	NG45 Fmax	NG45 Area	NG45 Pwr	ASAP7 Fmax	ASAP7 Area	ASAP7 Pwr	SKY130 Fmax	SKY130 Area	SKY130 Pwr
dfca64e	2ALU pMUL OoO LSU 9	76.01	915,409.21	9.82e-02	79.06	83,880.13	1.51e-02	29.70	4,836,589.92	6.61e-02
76143bb	RAS-4 + TAGE 10	62.08	1,037,535.66	9.17e-02	92.71	95,731.26	1.00e-02	28.65	5,494,031.71	7.48e-02
875aa2f	L2$ + L1I/SRAM 11	77.15	529,830.50	5.18e-02	94.79	49,517.43	1.22e-02	32.89	2,818,931.08	3.12e-02

RV64

Commit	Change	NG45 Fmax	NG45 Area	NG45 Pwr	ASAP7 Fmax	ASAP7 Area	ASAP7 Pwr	SKY130 Fmax	SKY130 Area	SKY130 Pwr
dfca64e	2ALU pMUL OoO LSU 9	46.67	1,531,961.83	1.11e-01	67.62	139,624.54	4.29e-03	21.02	8,115,397.06	1.04e-01
76143bb	RAS-4 + TAGE 10	27.82	1,695,775.00	1.02e-01	62.43	155,137.83	4.85e-03	16.14	9,027,255.35	1.21e-01
875aa2f	L2$ + L1I/SRAM 11	53.78	859,590.97	9.00e-02	57.67	80,248.39	6.80e-03	22.71	4,680,833.04	5.09e-02

Footnote [9] matches the corresponding entry in the CoreMark/MicroBench tables above. [10] and [11] STA were run via CI across all three PDKs and both ISAs. [10] used the default (dual-issue OoO) preset; [11] was measured at 875aa2f with the small (single-issue) preset, so its lower area/higher Fmax (e.g. RV32 NG45 area 1.04M -> 0.53M um^2, Fmax 62.08 -> 77.15 MHz) reflect the smaller preset, not a like-for-like uarch comparison. No STA result is recorded for the current default worktree 12.