Ecosystem

Simulators, FPGA boards, ASIC flow, software stack, and memory maps.

Supported Targets

Target	Purpose	Entry
NEMU	Software ISS (difftest reference)	`nemu/README.md`
NPC	Verilator simulator	`sim/`
FPGA	LiteX boards + Gowin Tang Nano	`fpga/litex/README.md`, `fpga/gowin-tang-nano-20k/README.md`
ASIC (open)	Yosys + OpenSTA flow	yosys-opensta

Simulators

Simulator	Role	Entry
NEMU	Software ISS, reference model	`make run-nemu32`, `nemu/`
NPC	Verilator, cycle-accurate, waveform	`make run-rv32`, `sim/`
raptSoC	SystemVerilog NPC top + AXI memory model	`sim/rtl/rapt_npc_soc.sv`

NPC is the primary development simulator. NEMU acts as the difftest reference for every commit.

FPGA Targets

Board / Flow	Status	Entry
MLK-CU08-KU15P / LiteX	Primary: Vivado, MIG DDR4, SD, CM005 Ethernet, RV32/RV64 Linux/netboot	`fpga/litex/`
MLK-CU07-KU15P / LiteX	Vivado, BIOS, MIG DDR4, SDCard, RV32 Linux boot	`fpga/litex/`
Alinx AXAU15 / LiteX	Vivado AU15P, auto-detected when that part is on the cable	`fpga/litex/`
Xilinx VCU118 / LiteX	Vivado VU9P, auto-detected when that part is on the cable	`fpga/litex/`
Tang Mega 138K Pro / LiteX	Gowin LiteX FPGA flow	`fpga/litex/`
Gowin Tang Nano 20K	Open-toolchain synth + P&R	`fpga/gowin-tang-nano-20k/`, `make fpga-syn`
OOC partitions	Frontend/backend/cache checkpoints, not a board flow	`fpga/ooc/README.md`

See fpga/litex/README.md for the LiteX BIOS + Linux flow.

ASIC Flow

Synthesis: Yosys with yosys-slang front-end for SystemVerilog.
STA: yosys-opensta — open-source static timing analysis (make sta).
PDK: open-source cell libraries; PPA results published under openppa.

See PROFILE.md for archived Freq / Power / Area results, Performance Iterations for recorded configuration-specific measurements, and REFERENCE.md for the PPA benchmark framework.

Software Stack

Layer	Component	Notes
App	CoreMark, MicroBench, Embench-IoT, busybox, demos	`app/`, `abstract-machine/app/`
User OS	nanos-lite (simple OS), Linux v6.18 userspace	`abstract-machine/app/nanos-lite`
ABI / libc	riscv-pk (proxy kernel), AM runtime, newlib, glibc	`app/pk/`, `abstract-machine/`
Kernel	Linux v6.18.51 prebuilt by default (`linux/vars.mk`)	`linux/`, see linux_kernel.md
Firmware	OpenSBI v1.8 (in-tree `third_party/.../opensbi`)	`linux/opensbi/`
Bootrom	NPC / raptSoC reset vector	`nemu/src/memory/rom/`

NPC Memory Map

npc_soc peripherals and address ranges:

Device	Range
Finisher	`0x0010_0000 – 0x0010_0fff`
CLINT	`0x0200_0000 – 0x020b_ffff`
PLIC	`0x0c00_0000 – 0x0cff_ffff`
SRAM	`0x0f00_0000 – 0x0f00_1fff`
UART / peripherals	`0x1000_0000 – 0x1001_1fff`
MROM	`0x2000_0000 – 0x2000_ffff`
Flash	`0x3000_0000 – 0x3fff_ffff`
PMEM (main memory)	`0x8000_0000 – 0x8fff_ffff`
SDRAM	`0xa000_0000 – 0xa1ff_ffff`

Reset vector PC_INIT = 0x2000_0000 (MROM).

Random Memory-Delay Simulation

Use make microbench-rv32 SIM_RANDOM_DELAY=31 or make coremark-rv64 SIM_RANDOM_DELAY=31 with SIM_RANDOM_DELAY=31 SIM_RANDOM_SEED=42 to exercise reproducible AXI memory wait states. cpu-tests-rv32 / cpu-tests-rv64 run AM CPU tests under the same delay model. These targets use the NPC memory map above.

Reference Device Trees

Spike

Source: riscv-isa-sim/riscv/platform.h

#define DEFAULT_RSTVEC     0x00001000
#define DEFAULT_ISA        "rv64imafdc_zicntr_zihpm"
#define DEFAULT_PRIV       "MSU"
#define CLINT_BASE         0x02000000
#define CLINT_SIZE         0x000c0000
#define PLIC_BASE          0x0c000000
#define PLIC_SIZE          0x01000000
#define NS16550_BASE       0x10000000
#define NS16550_SIZE       0x100
#define DRAM_BASE          0x80000000

QEMU (`virt`)

Source: hw/riscv/virt.c

[VIRT_CLINT]  = { 0x02000000, 0x00010000 },
[VIRT_PLIC]   = { 0x0c000000, VIRT_PLIC_SIZE(...) },
[VIRT_UART0]  = { 0x10000000, 0x00000100 },
[VIRT_FLASH]  = { 0x20000000, 0x04000000 },
[VIRT_DRAM]   = { 0x80000000, 0x00000000 },

NJU-ProjectN/NEMU — reference ISS.
NJU-ProjectN/abstract-machine — AM runtime.
riscv-software-src/opensbi — SBI firmware.
enjoy-digital/litex — FPGA SoC framework.
OpenXiangShan/XiangShan — inspirational reference.