Raptor — RISC-V Processor Core

The published homepage is an interactive product surface: a 2D pipeline block diagram extracted from the SystemVerilog tree, plus a documentation shell whose make commands come from the repository Makefile. This page is the written overview.

Raptor is a parameterized superscalar, out-of-order RISC-V core with register renaming, a reorder buffer, reservation stations, branch prediction, and Sv32/Sv39 virtual memory support for RV32/RV64.

The repository also bundles the NEMU software ISS (used as a difftest reference), a Verilator-based simulator (NPC), an AbstractMachine runtime, Linux kernel build scripts, and FPGA integration (Gowin Tang boards and Xilinx KU15P through LiteX).

Repository: https://github.com/Kingfish404/raptor-chip

Core Summary

See Microarchitecture for the complete pipeline description.

Performance (Verilator, RV32EM, bare-metal)

See Performance Iterations for the recorded IPC history of the current two-wide configuration. PROFILE is a legacy archive and does not describe the default RTL.

Verification

• Difftest — retired instructions can be compared against NEMU, including the full-core directed/differential RV32/RV64 F/D test suite under app/tests/fp.
• Architectural tests — cpu-tests supplies RV32/RV64 smoke coverage; historical pass counts do not certify the current working tree.
• RISCOF running riscv-arch-test: classic test entry points compare signatures with Sail for the RTL DUT (make verify-riscof-classic) and NEMU (make verify-riscof-classic-nemu). The classic profile declares RV32 I/M/A/F/D/C/S/U plus the listed Z extensions. ACT4 has separate RV32GC, RV64GC M-mode and RV64 supervisor configurations; see verification. The riscv-dv target is an RV32 I/M/C, M-mode, Bare smoke configuration.
• Benchmarks: CoreMark, MicroBench, Embench-IoT, and RLLMBench/LLM-style fixed-point workloads under NPC/NEMU and selected native/LiteX paths.
• System software: nanos-lite, riscv-pk, OpenSBI + Linux boot (see Linux Kernel Boot); upstream xv6-riscv and egos-2000 CLI smoke paths are available through app/tinyos.

Documentation

• Quick Start — build and simulate.
• Microarchitecture — pipeline, modules, interfaces, ISA breakdown.
• Profile — benchmarks, cycle-stall breakdown, PPA.
• Performance Iterations — IPC history per commit.
• Ecosystem — simulators, SoC memory maps, FPGA, tools.
• Linux Kernel Boot — OpenSBI + Linux on NEMU / NPC.
• Standalone VPU — RVV 1.0 component delivery; not yet integrated into the scalar core.
• Reference — AXI4, PPA references.

Repository Layout

raptor-chip/
├── Makefile              top-level driver
├── env.sh                environment variables (auto-sourced by Makefile)
├── hdl/                   SystemVerilog RTL
│   ├── chisel/            Chisel decoder generator
│   ├── rapt.sv           cluster-level top (core + CLINT + PLIC + router + debug)
│   ├── rapt_core.sv      single-hart CPU body
│   ├── rapt_pkg.sv       core configuration and shared types
│   ├── frontend/         IFU, FQU, IDU, RNU, BPU, CSR
│   ├── backend/          PRF, ROU, DPU, IEU, FEU, LSU, CMU
│   ├── memory/           L1I/L1D, optional L2, TLB, PTW, AXI4 bus
│   ├── perip/            CLINT, PLIC, debug module, JTAG DTM, DPI wrappers
│   ├── include/          type macros, interfaces, DPI-C
│   └── generated/        Chisel-generated decoders
├── nemu/                 NEMU reference ISS
├── sim/                  NPC Verilator simulator
├── lspd/                 synthesis/PPA flow and non-product HDL wrappers
├── abstract-machine/     AM runtime (nanos-lite, navy-apps)
├── linux/                Linux kernel build scripts
├── fpga/                 FPGA integration (Gowin Tang Nano 20K, LiteX)
└── docs/                 documentation (this directory)

The project is licensed under the Apache License 2.0. Third-party components retain their original licenses; see NOTICE.